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Specifications |
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- Double
Data Rate architecture
- Bandwidth(max):
2.1GB/s; 2.7GB/s; 3.2GB/s
- JEDEC
standard
- 2
Banks to be operated simultaneously or
independently
- Serial
Presence Detect support
- Universal
bus driver is designed for 2.3V to 2.7V
- MRS
cycle with address key programs
* CAS latency: 2, 2.5 & 3 (clock)
* Burst length: 2, 4 & 8
* Burst type: Sequential & Interleave
- 2
variations of refresh
* Auto refresh
* Self refresh
- Stabilization
time to achieve the PLL clock driver
- Serial Presence
Detect support
- Low Profile PCB
available
- Minimum Propagation delay of the Address-Bus
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